Title :
A floorplan method for asynchronous circuits with bundled-data implementation on FPGAs
Author :
Saito, Hiroshi ; Hamada, Naohiro ; Yoneda, Tomohiro ; Nanya, Takashi
Author_Institution :
Univ. of Aizu, Aizu-Wakamatsu, Japan
fDate :
May 30 2010-June 2 2010
Abstract :
This paper proposes a floorplan method for asynchronous circuits with bundled-data implementation on FPGAs. The proposed method minimizes the delay of the control circuit while considering timing constraints required for bundled-data implementation. Through the implementation of the proposed method, this paper evaluates the proposed method in terms of performance and area for generated floorplans.
Keywords :
asynchronous circuits; circuit layout; delays; field programmable gate arrays; FPGA; asynchronous circuits; control circuit; delay; floorplan method; timing constraints; Asynchronous circuits; Circuit synthesis; Delay estimation; Energy consumption; Field programmable gate arrays; Informatics; Logic circuits; Signal generators; Time factors; Timing;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537402
