DocumentCode
3379122
Title
Case Study: GPU-based implementation of sequence pair based floorplanning using CUDA
Author
Choi, Won Ha ; Liu, Xun
Author_Institution
Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
fYear
2010
fDate
May 30 2010-June 2 2010
Firstpage
917
Lastpage
920
Abstract
In this paper, we demonstrate that runtime of VLSI Computer-aided design (CAD) applications can be successfully reduced with parallel programming in conjunction with Graphic Processing Units (GPUs). Particularly, we apply GPU-based computing to the sequence pair based floorplanning algorithm. In addition to reducing runtime, we focus on the minimization of changes in code structure in order to reduce programming efforts. With less than 16 percent of the original program modified, the runtime of the floorplanning algorithm shows an average speedup of 13.5 without performance degradation.
Keywords
VLSI; circuit layout CAD; computer graphic equipment; integrated circuit design; integrated circuit layout; microprocessor chips; CAD; CUDA; GPU; VLSI computer-aided design; code structure; graphic processing units; parallel programming; sequence pair based floorplanning algorithm; Concurrent computing; Degradation; Design automation; Graphics processing unit; Multicore processing; Parallel programming; Runtime; Simulated annealing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location
Paris
Print_ISBN
978-1-4244-5308-5
Electronic_ISBN
978-1-4244-5309-2
Type
conf
DOI
10.1109/ISCAS.2010.5537405
Filename
5537405
Link To Document