Title :
Logic circuit extraction for bridging fault equivalence identification in CMOS ICs
Author :
Simões, M.C. ; Teixeira, I.M. ; Teixeira, J.P.
Author_Institution :
INESC, ISEL, ISCTE, IST, Lisboa, Portugal
Abstract :
A new methodology for test preparation, at gate level, is introduced. Realistic bridging faults between logical nodes are used as a fault model. The methodology requires logic circuit extraction, from the transistor circuit netlist: hence, a new logic extractor for static CMOS designs, tabloid, is presented. Preliminary results on logic extraction, and bridging fault equivalence identification are presented
Keywords :
CMOS integrated circuits; integrated circuit testing; logic testing; CMOS ICs; bridging fault equivalence identification; logic circuit extraction; tabloid; Automatic test pattern generation; CMOS logic circuits; CMOS technology; Circuit faults; Circuit testing; Costs; Fault diagnosis; Logic circuits; Logic testing; Semiconductor device modeling;
Conference_Titel :
European Test Conference, 1993. Proceedings of ETC 93., Third
Conference_Location :
Rotterdam
Print_ISBN :
0-8186-3360-3
DOI :
10.1109/ETC.1993.246620
