Logic circuit extraction for bridging fault equivalence identification in CMOS ICs

Author

Simões, M.C. ; Teixeira, I.M. ; Teixeira, J.P.

Author_Institution

INESC, ISEL, ISCTE, IST, Lisboa, Portugal

fYear

1993

fDate

19-22 Apr 1993

Firstpage

538

Lastpage

539

Abstract

A new methodology for test preparation, at gate level, is introduced. Realistic bridging faults between logical nodes are used as a fault model. The methodology requires logic circuit extraction, from the transistor circuit netlist: hence, a new logic extractor for static CMOS designs, tabloid, is presented. Preliminary results on logic extraction, and bridging fault equivalence identification are presented

Keywords

CMOS integrated circuits; integrated circuit testing; logic testing; CMOS ICs; bridging fault equivalence identification; logic circuit extraction; tabloid; Automatic test pattern generation; CMOS logic circuits; CMOS technology; Circuit faults; Circuit testing; Costs; Fault diagnosis; Logic circuits; Logic testing; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

European Test Conference, 1993. Proceedings of ETC 93., Third

Conference_Location

Rotterdam

Print_ISBN

0-8186-3360-3

Type

conf

DOI

10.1109/ETC.1993.246620

Filename

246620

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3379123