STI stress-induced degradation of data retention time in DRAM and a new characterizing method for mechanical stress

Author

Jang, Tae-Su ; Kim, Kyung-do ; Yoo, Min-Soo ; Kim, Yong-Taik ; Cha, Seon-Yong ; Jeong, Jae-Goan ; Hong, Sung-Joo

Author_Institution

R&D Div., Hynix Semicond. Inc., Icheon, South Korea

fYear

2011

fDate

10-14 April 2011

Abstract

The effect of mechanical stress induced by shallow trench isolation (STI) slope on the data retention characteristics of DRAM is investigated and a new electrical parameter for monitoring the mechanical stress is proposed. To maintain high and uniform retention time for the reliable operation of DRAM, the STI slope should not be vertical and should be kept below 86-degree. The new electrical parameter measures the current gain of the parasitic BJT in DRAM cell and shows a strong correlation with the retention time induced by the mechanical stress.

Keywords

DRAM chips; bipolar transistors; stress analysis; DRAM; STI slope; STI stress-induced degradation; data retention time; mechanical stress effect; parasitic BJT; shallow trench isolation; Correlation; Junctions; Monitoring; Random access memory; Silicon; Stress; Tin; DRAM; Data retention time; Mechanical stress; shallow trench isolation (STI);

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2011 IEEE International

Conference_Location

Monterey, CA

ISSN

1541-7026

Print_ISBN

978-1-4244-9113-1

Electronic_ISBN

1541-7026

Type

conf

DOI

10.1109/IRPS.2011.5784458

Filename

5784458