DocumentCode :
3379209
Title :
A novel approach for simultaneous reduction of shift and capture power for scan based testing
Author :
Sivanantham, S. ; Sandeep, Vuddanti ; Mallick, P.S. ; Perinbam, J.R.P.
Author_Institution :
Sch. of Electron. Eng., VIT Univ., Vellore, India
fYear :
2011
fDate :
21-22 July 2011
Firstpage :
418
Lastpage :
423
Abstract :
This paper proposes a novel approach for reducing the shifting and capture power by a fan-out aware modified adjacent X-filling technique. This approach reduces the time complexity and number of iterations in addition to the reduction of test power. Experimental results obtained from ISCAS´89 circuits are compared with existing techniques prove that the proposed ATPG methodology is suitable to test the scan based system-on-chip architecture with reduced testing power.
Keywords :
automatic test pattern generation; computational complexity; integrated circuit testing; system-on-chip; ATPG methodology; fan-out aware modified adjacent X-filling technique; scan based system-on-chip architecture; scan based testing; simultaneous reduction; time complexity; Automatic test pattern generation; Filling; Power dissipation; Switches; Switching circuits; Very large scale integration; Capture power; Design for Testability; Scan based testing; Shift Power; low power;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signal Processing, Communication, Computing and Networking Technologies (ICSCCN), 2011 International Conference on
Conference_Location :
Thuckafay
Print_ISBN :
978-1-61284-654-5
Type :
conf
DOI :
10.1109/ICSCCN.2011.6024587
Filename :
6024587
Link To Document :
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