DocumentCode :
3379254
Title :
Low power, low area and high Performance Hybrid Type DYNAMIC CAM design
Author :
Nagarjuna, V. ; Kittur, Harish M.
Author_Institution :
Sch. of Electron. Eng., VIT Univ., Vellore, India
fYear :
2011
fDate :
21-22 July 2011
Firstpage :
430
Lastpage :
435
Abstract :
Content-addressable memories (CAMs) are hardware search engines that are much faster than algorithmic approaches for search-intensive applications. CAMs are composed of conventional semiconductor memory (usually SRAM) with added comparison circuitry that enables a search operation to complete in a single clock cycle In case of advanced applications we need large sized CAM but it has the disadvantage of high power consumption. To overcome the drawbacks we need to reduce the power consumption of the CAM when we search the data. This paper proposes an idea for improving power, area and performance of the system of recently proposed high Performance Hybrid-Type CAM Designs. For this we replace the basic 9T CAM cell with a 4T CAM cell. The simulation results show the success of the method.
Keywords :
SRAM chips; content-addressable storage; search engines; 4T CAM cell; 9T CAM cell; SRAM; added comparison circuitry; content-addressable memories; hardware search engines; high performance hybrid type dynamic CAM design; low area hybrid type dynamic CAM design; low power hybrid type dynamic CAM design; semiconductor memory; Arrays; Computer aided manufacturing; Delay; Discharges; Educational institutions; Heuristic algorithms; Random access memory; 4T CAM cell; Basic 9T CAM cell; Hybrid CAM Design; NAND-Type Array; NOR-Type Array;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signal Processing, Communication, Computing and Networking Technologies (ICSCCN), 2011 International Conference on
Conference_Location :
Thuckafay
Print_ISBN :
978-1-61284-654-5
Type :
conf
DOI :
10.1109/ICSCCN.2011.6024589
Filename :
6024589
Link To Document :
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