DocumentCode
3379320
Title
An efficient VLSI architecture for variable threshold simple edge preserved denoising algorithm with improved signal to noise ratio
Author
Praneeth, P. ; Sakthivel, Rathinasamy ; Reddy, S. Sumanth Kumar ; Kittur, Harish M.
Author_Institution
VIT Univ., Vellore, India
fYear
2011
fDate
21-22 July 2011
Firstpage
448
Lastpage
453
Abstract
Image acquisition and transmission stands challenging in applications such as medical imaging, underwater imaging, image segmentation and face recognition where images are often corrupted by impulse noise. The key aim is to reduce the impulse noise effectively by less number of computations, less memory, less power consumption and yet achieving good visual quality of the images compared to the existing techniques. In this paper, a new intelligent low cost hardware module suitable for reduction of impulse noise is proposed. The technique which we follow here is Improved Simple Edge Preserved Denoising (ISEPD) technique with variable threshold. Simulation results show that the PSNR has improved compared to other previous techniques. Synthesis results show that the processing rate is 133 M samples/second by using TSMC 0.18μm technology.
Keywords
VLSI; image denoising; image segmentation; impulse noise; ISEPD; VLSI architecture; face recognition; image acquisition; image segmentation; image transmission; impulse noise; medical imaging; underwater imaging; variable threshold simple edge preserved denoising algorithm; Detectors; Hardware; Image edge detection; Noise; Noise measurement; Pipelines; Registers; Image denoising; Image processing; Impulse noise; VLSI; variable threshold;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing, Communication, Computing and Networking Technologies (ICSCCN), 2011 International Conference on
Conference_Location
Thuckafay
Print_ISBN
978-1-61284-654-5
Type
conf
DOI
10.1109/ICSCCN.2011.6024592
Filename
6024592
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