DocumentCode
3379342
Title
Design of resistant DPA three-valued counter based on SABL
Author
Zhang, Yuejun ; Wang, Pengjun ; Hao, Lipeng
Author_Institution
Inst. of Circuits & Syst., Ningbo Univ., Ningbo, China
fYear
2011
fDate
25-28 Oct. 2011
Firstpage
9
Lastpage
12
Abstract
Through studying the design principles of multi-valued logic circuit and the SABL circuit, this paper presents a design scheme of three-valued counter. Two-valued coding method and SABL circuit characteristics such as complementary output signals and the capacitance coupling effect are integrated to implement the developed scheme. Then, the current compensation circuit is used to keep steady output logic 1, and further to achieve n-bit three-valued counter. Finally, with the parameters of SMIC 0.13μm CMOS device, the SABL three-valued counter is simulated by SPECTRE. The results show that the designed circuit has correct logic function and constant power per clock cycle.
Keywords
CMOS logic circuits; counting circuits; encoding; SABL; SABL circuit characteristics; SABL three-valued counter; SMIC 0.13 μm CMOS device; SPECTRE; achieve n-bit three-valued counter; capacitance coupling effect; complementary output signal; current compensation circuit; differential power analysis; logic function; multivalued logic circuit; resistant DPA three-valued counter; sense amplifier based logic; size 0.13 mum; steady output logic 1; two-valued coding method; Cryptography; Integrated circuits; DPA; Multivalued logic; SABL; Three-valued counter;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC (ASICON), 2011 IEEE 9th International Conference on
Conference_Location
Xiamen
ISSN
2162-7541
Print_ISBN
978-1-61284-192-2
Electronic_ISBN
2162-7541
Type
conf
DOI
10.1109/ASICON.2011.6157109
Filename
6157109
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