A reconfigurable macro-pipelined DCT/IDCT accelerator

Author

Bao, Wenqi ; Jiang, Jiang ; Sun, Qing ; Fu, Yuzhuo

Author_Institution

Sch. of Microelectron., Shanghai Jiao Tong Univ., Shanghai, China

fYear

2011

fDate

25-28 Oct. 2011

Firstpage

25

Lastpage

28

Abstract

In this paper, a reconfigurable macro-pipelined (RMP) accelerator is proposed to speed up the Discrete Cosine Transform (DCT) and Inverse Discrete Cosine Transform (IDCT). The accelerator can be reconfigured to compute fixed-point or floating-point, one-dimensional or multi-dimensional DCT/IDCT according to different system requirements. The prototype is implemented on Xilinx ML605 experiment board with 64 PEs. It takes 64 cycles at 200MHz to complete an 8×8 2D DCT and gets a peak performance of 25.6 GFLOPS for the floating-point DCT. The excellent scalability of this architecture enables the accelerator to scale up to an extremely high performance.

Keywords

discrete cosine transforms; field programmable gate arrays; floating point arithmetic; graphics processing units; pipeline arithmetic; Xilinx ML605; computer speed 25.6 GFLOPS; discrete cosine transform; floating-point DCT; frequency 200 MHz; inverse discrete cosine transform; reconfigurable macro-pipelined DCT/IDCT accelerator; Computer languages; Discrete cosine transforms;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC (ASICON), 2011 IEEE 9th International Conference on

Conference_Location

Xiamen

ISSN

2162-7541

Print_ISBN

978-1-61284-192-2

Electronic_ISBN

2162-7541

Type

conf

DOI

10.1109/ASICON.2011.6157113

Filename

6157113