Impact of process variations on bus-encoding schemes for delay minimization in VLSI interconnects

Process variations can have a significant impact on both device and interconnect performance in deep submicron (DSM) technologies. In this paper, authors discuss the impact of process parameter variations on bus-encoding schemes for delay minimization. It is shown that if process variability is taken into consideration, there will be a change in effective capacitance (Ceff) of the bus lines because of which the amount of delay that each crosstalk class causes is going to vary. SPICE simulations have been carried out for interconnect lines (three bit bus model) of different dimensions at different technology nodes (180, 130, 90 and 65 nm) to find out the effect of process variability on the effective capacitance of bus lines. Finally, the impact of process variations on bus-encoding schemes for delay minimization is discussed in detail.