ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs

This work proposes an ADDLL/VDD-biasing co-design methodology for variation-tolerant designs. A modified ADDLL behaves as a variability sensor in the beginning of operation, and the sensing result is used by a VDD-biasing circuit to adjust the VDD of a loaded design for performance calibration. During normal operation, the ADDLL is reused as a de-skewing element for the calibrated design. With this methodology, not only the performance of the loaded design but also that of the ADDLL can be effectively adjusted toward their design specifications even under serious process variations.