An instruction set for a programmable signal processor dedicated to Viterbi detection

A programmable Viterbi signal processor (VSP) for the efficient implementation of sequence detection, most notably the Viterbi algorithm, is presented. The VSP architecture and instruction set introduced permits the efficient software implementation of decoders for most popular trellis codes, convolutional codes, and partial-response channels at rates ten to one hundred times faster than those achievable on conventional digital signal processors. Multidimensional trellis decoding can be implemented at sampling rates approaching 1 MHz in software on the VSP. The VSP contains three concurrent and independently programmable subprocessors. The architecture of the VSP is described. This paper´s emphasis is on the programming of the VSP