A video buffer controller design for HDTV/BISDN system

Author

Liau, Shyi-Ching

Author_Institution

CCL/ITRI, Hsin-Chu, Taiwan

fYear

1991

fDate

22-24 May 1991

Firstpage

237

Lastpage

241

Abstract

Represents the design of a video buffer controller for an HDTV/BISDN experimental research prototype which demonstrates digital HDTV coding and transport at STS-3c rate within an ATM payload of 130 Mb/s. With a generic design, this video buffer controller would be suitable both for the transmitting end and the receiving end. A nibble-wide quaternary data processing algorithm is introduced to make it possible for the system to interface with commercial memory available today to accommodate with a high data rate processing. Some other functions, such as calculation and reporting of buffer occupancy, address jumping and alarm flag generation, are also provided

Keywords

B-ISDN; asynchronous transfer mode; codecs; high definition television; 130 Mbit/s; ATM payload; HDTV/BISDN system; STS-3c rate; address jumping; alarm flag generation; buffer occupancy; digital HDTV coding; nibble-wide quaternary data processing algorithm; receiving end; transmitting end; video buffer controller design; Buffer overflow; Buffer storage; Codecs; Control systems; Decoding; Entropy; HDTV; Optical buffering; Optical feedback; Optical transmitters;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 1991. Proceedings of Technical Papers, 1991 International Symposium on

Conference_Location

Taipei

ISSN

1524-766X

Print_ISBN

0-7803-0036-X

Type

conf

DOI

10.1109/VTSA.1991.246674

Filename

246674