DocumentCode
3379680
Title
A two-way parallel CAVLC encoder for 4K×2K H.264/AVC
Author
Zhong, Huibo ; Shen, Sha ; Fan, Yibo ; Zeng, Xiaoyang
Author_Institution
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
fYear
2011
fDate
25-28 Oct. 2011
Firstpage
75
Lastpage
78
Abstract
This paper presents a high performance design for Context-Based Adaptive Variable Length-Coding (CAVLC) used in the H.264/AVC standard. To reduce the cycles of processing one macroblock (MB), a two-stage residual encoder is proposed to make the scan and encode stage work simultaneously. The scan engine scans two coefficients at each cycle. Parallel encoder for two levels and parallel encoder for two runs are adopted to accelerate the encoder engine. Only 228 cycles at most are needed to process one MB. Due to the existence coded block pattern (CBP) decided skip block mode, our experiment shows only 160 cycles are needed on the average. The proposed CAVLC encoder can support 4K×2K @30fps (frames per second) real-time encoding at 250 MHz and the gate count is only about 16k.
Keywords
adaptive codes; data compression; variable length codes; video coding; CBP; H.264-AVC standard; coded block pattern; context-based adaptive variable-length coding; encode stage; encoder engine; frequency 250 MHz; gate count; high-performance design; macroblock; real-time encoding; scan engine; scan stage; two-stage residual encoder; two-way parallel CAVLC encoder; Computer architecture; Levee; CAVLC; H.264/AVC; entropy encoding; level encoder;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC (ASICON), 2011 IEEE 9th International Conference on
Conference_Location
Xiamen
ISSN
2162-7541
Print_ISBN
978-1-61284-192-2
Electronic_ISBN
2162-7541
Type
conf
DOI
10.1109/ASICON.2011.6157126
Filename
6157126
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