DocumentCode
3379828
Title
Simulation of P- and N-MOSFET hot-carrier degradation in CMOS circuits
Author
Lee, Peter M. ; Garfinkel, Tom ; Ko, Ping K. ; Hu, Chenming
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fYear
1991
fDate
22-24 May 1991
Firstpage
191
Lastpage
195
Abstract
A PMOSFET hot-carrier degradation model has been incorporated into the reliability simulator BERT-CAS, enabling prediction of dynamic circuit-level degradation in which both PMOSFET and NMOSFET degradation play a major role. Comparisons are presented which reveal the good fit obtained between measurement and simulation results
Keywords
CMOS integrated circuits; circuit analysis computing; hot carriers; insulated gate field effect transistors; semiconductor device models; BERT-CAS; CMOS circuits; NMOSFET; PMOSFET; dynamic circuit-level degradation; hot-carrier degradation; model; reliability simulator; Aging; Circuit simulation; Computational modeling; Content addressable storage; Degradation; Hot carriers; MOSFET circuits; Predictive models; Semiconductor device modeling; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems, and Applications, 1991. Proceedings of Technical Papers, 1991 International Symposium on
Conference_Location
Taipei
ISSN
1524-766X
Print_ISBN
0-7803-0036-X
Type
conf
DOI
10.1109/VTSA.1991.246684
Filename
246684
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