Implementation of low power RAM in GDI technique with full swing

Author

Kannan, P. Magesh ; Prathyusha, K.

Author_Institution

VLSI Div., VIT Univ., Vellore, India

fYear

2011

fDate

21-22 July 2011

Firstpage

592

Lastpage

597

Abstract

Low power design has become one of the primary focuses in digital VLSI circuits. Technology scaling demands a decrease in both supply voltage (V_DD) and threshold voltage (V_TH). This leads to increase in sub-threshold leakage power. In VLSI chips, the power consumption is more in Flip-Flops. So the primary objective of using sub-threshold circuits is to reduce the energy. This paper presents about a low power RAM implemented in the proposed Gate-Diffusion-Input (GDI) technique that provides full swing. The design is simulated in 0.18μm TSMC technology with the supply voltage of 1.8V using Mentor Graphics Design Architect.

Keywords

VLSI; flip-flops; low-power electronics; random-access storage; GDI technique; VLSI chips; digital VLSI circuit; flip-flops; gate-diffusion-input technique; low power RAM; mentor graphics design architect; subthreshold leakage power; supply voltage; technology scaling; threshold voltage; CMOS integrated circuits; Decoding; Flip-flops; Logic gates; Random access memory; Threshold voltage; Transistors; Flip-Flops; Full swing; GDI technique; Low power; RAM; Sequential circuits; Sub threshold region; VLSI;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing, Communication, Computing and Networking Technologies (ICSCCN), 2011 International Conference on

Conference_Location

Thuckafay

Print_ISBN

978-1-61284-654-5

Type

conf

DOI

10.1109/ICSCCN.2011.6024620

Filename

6024620