Electromigration induced void kinetics in Cu interconnects for advanced CMOS nodes

Time evolution of resistance during EM tests is extensively analyzed for various Cu interconnect structures and processes from the 40 nm node technology. Resistance evolution is used to model void nucleation and growth kinetics. We show that adding Al or other impurities in the line is effective to increase electromigration lifetime. This lifetime increase is due, as expected, to Cu drift velocity decrease but also to an increase of the time to void formation. TEM picture shows that Al precipitates are formed at grain boundaries and are most likely responsible for the occurrence of an incubation time Resistance saturation is observed for short lines thanks to Blech effect. A resistance model is developed to characterize short length effect in 40 nm node. The model is also used to explain EM lifetime improvement thanks to a pre-stress condition where compressive stress is added at cathode end of long line structures.