Evaluation driven layout synthesis

Author

Wu, Allen C-H ; Gajski, Daniel D. ; Chen, Gwo-Dong

Author_Institution

Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA

fYear

1991

fDate

22-24 May 1991

Firstpage

167

Lastpage

171

Abstract

The authors describe a layout synthesis system for layout generation from generalized register-transfer schematics. This system uses the SLAM partitioner and the ICDB component server. The system is performed in a completely top-down manner which generates the layout by considering the component layout style, floorplan, and critical paths simultaneously. This improves the overall area utilization and minimizes the critical wire lengths, which in turn yields better performance

Keywords

VLSI; circuit layout CAD; logic CAD; ICDB component server; SLAM partitioner; VLSI; component layout style; critical paths; critical wire lengths; evaluation driven layout synthesis; floorplan; generalized register-transfer schematics; intelligent component database; layout generation; layout synthesis system; silicon compiler; Computer science; Digital signal processing chips; Flip-flops; Multiplexing; Registers; Routing; Simultaneous localization and mapping; Switches; Very large scale integration; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 1991. Proceedings of Technical Papers, 1991 International Symposium on

Conference_Location

Taipei

ISSN

1524-766X

Print_ISBN

0-7803-0036-X

Type

conf

DOI

10.1109/VTSA.1991.246689

Filename

246689