Calibration Technique for σΔ Modulation Loops using Radio-Frequency Phase Detection

A novel calibration scheme for predistortion ΣΔPLLs is proposed in this paper. In contrast to present calibration algorithms this technique offers a digital representation of the high frequency phase characteristic. The architecture uses minimum chip area by synchronously sampling the data content of an asynchronous divider chain. Using this technique to detect the phase difference during a step response allows to determine the real loop gain within 7 mus with an accuracy better than 0.1%. Obtaining this, the deviation from the desired loop gain can be adjusted by a digitally controlled charge pump in order to derive the wanted loop transfer function. This is mandatory for predistortion modulation loops. The architecture is designed by systemtheoretical calculation of the loop behaviour and verified by mixed signal VHDL-AMS simulations.