Supervised learning in a two-input analog floating-gate node

We pursue the realization of on-chip supervised learning networks for large-scale, real-time signal processing applications using array of analog floating-gate synapses. We present experimental data characterizing the performance of a two-input analog floating-gate pFET synapse network that implements a supervised learning algorithm similar to the least-mean square (LMS) learning rule; most other supervised learning algorithm possess a straight-forward relation to the LMS algorithm. Analog floating-gate synapses enable larger-sale, on-chip learning networks than previously possible.