DocumentCode
3380220
Title
Design of four-transistor Pixel for high speed CMOS image
Author
Yangfan, Zhou ; Zhongxiang, Cao ; Li Quanliang ; Qi, Qin ; Nanjian, Wu
Author_Institution
State Key Lab. for Superlattices & Microstructures, Inst. of Semicond., Beijing, China
fYear
2011
fDate
25-28 Oct. 2011
Firstpage
171
Lastpage
174
Abstract
This paper designs and tests a series of high speed four-transistor Pixels with 0.13μm CMOS process. The prototype sensor contains 256×128 pixels with 8 different pixel architectures. Pixel size is 10μm×10μm. The measured sensitivity is 17.3V/lux·s, conversion gain is 49.6μV/e-, non-linearity is 3.6%, read noise is 23e- and dynamic range is 60dB. The optimizing design effectively improves the performance of high speed four-transistor Pixel.
Keywords
CMOS image sensors; high-speed optical techniques; integrated circuit noise; high speed CMOS image; high speed four-transistor pixels; pixel architectures; prototype sensor; read noise; size 0.13 mum; CMOS integrated circuits; CMOS technology; Gain; Impurities; Semiconductor device measurement; Video equipment;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC (ASICON), 2011 IEEE 9th International Conference on
Conference_Location
Xiamen
ISSN
2162-7541
Print_ISBN
978-1-61284-192-2
Electronic_ISBN
2162-7541
Type
conf
DOI
10.1109/ASICON.2011.6157149
Filename
6157149
Link To Document