DocumentCode
3380261
Title
Transient latchup in power analog circuits
Author
Vashchenko, V.A. ; Lafonteese, D. ; Concannon, A.
Author_Institution
Nat. Semicond. Corp., Santa Clara, CA, USA
fYear
2011
fDate
10-14 April 2011
Abstract
Two cases of transient latchup specific to power management analog integrated circuit design are described and analyzed experimentally. The representative case studies include the interaction of a power array and ESD clamp and the interaction of two high voltage ESD clamps.
Keywords
analogue integrated circuits; clamps; electrostatic discharge; flip-flops; integrated circuit design; analog integrated circuit design; high voltage ESD clamp; power analog circuit; power array; power management; transient latchup; Arrays; Clamps; Electrostatic discharge; Logic gates; Pins; Transient analysis; Voltage control; ESD; TLP; analog; latchup; power;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium (IRPS), 2011 IEEE International
Conference_Location
Monterey, CA
ISSN
1541-7026
Print_ISBN
978-1-4244-9113-1
Electronic_ISBN
1541-7026
Type
conf
DOI
10.1109/IRPS.2011.5784508
Filename
5784508
Link To Document