DocumentCode
3380291
Title
A subnanosecond clamped-bit-line sense amplifier for 1T dynamic RAMs
Author
Blalock, Travis N. ; Jaeger, Richard C.
Author_Institution
Dept. of Electr. Eng., Auburn Univ., AL, USA
fYear
1991
fDate
22-24 May 1991
Firstpage
82
Lastpage
86
Abstract
A clamped-bit-line sense amplifier (CBLSA) capable of subnanosecond response in 1T DRAM applications has been developed. Results from an experimental test chip demonstrate that the speed of the new circuit is insensitive to bit line capacitance. The CBLSA maintains a low impedance fixed potential on the bit lines, virtually eliminating sensitivity to inter-bit-line noise coupling and minimizing power supply bounce during sensing
Keywords
DRAM chips; amplifiers; circuit reliability; DRAM applications; charge sensing; clamped-bit-line sense amplifier; low impedance fixed potential; power supply bounce; subnanosecond response; Capacitance; Circuit noise; Circuit testing; Clamps; Coupling circuits; Impedance; Microelectronics; Power supplies; Read-write memory; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems, and Applications, 1991. Proceedings of Technical Papers, 1991 International Symposium on
Conference_Location
Taipei
ISSN
1524-766X
Print_ISBN
0-7803-0036-X
Type
conf
DOI
10.1109/VTSA.1991.246706
Filename
246706
Link To Document