A 2.2mW CMOS LNA for 6–8.5GHz UWB receivers

This paper presents an ultra-wideband (UWB) low noise amplifier (LNA) consuming 2.2-mW core dc power for 6-8.5GHz wireless applications. A common-gate input stage is cascaded with a common-source second stage to perform input impedance matching and wideband stagger-tuning amplification, while the current-reuse topology minimizes the dc power dissipation. The design method used to achieve flat-gain response is presented. A detailed analysis gives insight into the issue on the input impedance and suggests a solution. Implemented in a 90-nm CMOS process, the measurement results show power gain of 13.35+/-0.55 dB, input third intercept point (IIP3) of-6.2 dBm, and noise figure of 5-6.5 dB. The silicon die with 0.22-mm² active area allows the design to be adopted for highly integrated low-cost CMOS applications.