A multichip analog neural network

Author

Van der Spiegel, J. ; Mueller, P. ; Agami, V. ; Aziz, P. ; Blackman, D. ; Chance, P. ; Choudhury, A. ; Donham, C. ; Etienne-Cummings, R. ; Jones, L. ; Kim, J. ; Kinget, P. ; Massa, M. ; von Koch, W. ; Xin, J.

Author_Institution

Dept. of Electr. Eng. & Biophys., Pennsylvania Univ., Philadelphia, PA, USA

fYear

1991

fDate

22-24 May 1991

Firstpage

64

Lastpage

68

Abstract

A multichip, programmable analog neural network for real-time dynamic computations is described. The network´s interconnection structure, the neuron characteristics, synaptic connections, and synaptic time constant are modifiable. The chips are designed to allow a modular and expandable gross architecture that can be adjusted to the complexity of the task. The network operates fully analog in real time. However, a digital host is used to set the network parameters and monitor the neuron outputs. A prototype neural computer consisting of 72 neurons has been assembled and tested. The network has been successfully configured for several applications and found to have a performance that is equivalent to a digital machine of 10¹¹ FLOPS

Keywords

neural chips; neural nets; parallel architectures; real-time systems; 10¹¹ FLOPS; digital host; expandable gross architecture; interconnection structure; modular architecture; multichip analog neural network; neuron characteristics; programmable analog neural network; prototype neural computer; real-time dynamic computations; synaptic connections; synaptic time constant; Analog computers; Assembly; Computer architecture; Computer networks; Computerized monitoring; Condition monitoring; Neural networks; Neurons; Prototypes; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 1991. Proceedings of Technical Papers, 1991 International Symposium on

Conference_Location

Taipei

ISSN

1524-766X

Print_ISBN

0-7803-0036-X

Type

conf

DOI

10.1109/VTSA.1991.246710

Filename

246710