Title :
A 40 Gb/s transimpedance amplifier in 65 nm CMOS
Author :
Bashiri, Samira ; Plett, Calvin ; Aguirre, Jorge ; Schvan, Peter
Author_Institution :
Dept. of Electron., Carleton Univ., Ottawa, ON, Canada
fDate :
May 30 2010-June 2 2010
Abstract :
A 40 Gb/s transimpedance amplifier (TIA) is designed as a modified regulated cascode in 65 nm CMOS technology using ultra-compact peaking inductors to provide improved frequency response and lower input referred noise. The bandwidth of the TIA is 21.6 GHz with 46.7 dBΩ of gain for an input capacitance of 200 fF and the simulated input referred noise is below 30pA/√(Hz) up to 26.1 GHz. The TIA core occupies only 150 μm×50 μm of chip area and for a 1.2 V supply voltage the TIA consumes 8.2 mW while the power-hungry buffers need 31.5 mW to drive the 50 Ω load. The TIA is measured in a 50 Ω environment.
Keywords :
CMOS analogue integrated circuits; frequency response; inductors; operational amplifiers; CMOS technology; bandwidth 21.6 GHz; bit rate 40 Gbit/s; capacitance 200 fF; frequency response; lower input referred noise; power 31.5 mW; power 8.2 mW; resistance 50 ohm; size 65 nm; transimpedance amplifier; ultra-compact peaking inductors; voltage 1.2 V; Bandwidth; CMOS technology; Capacitance; Ethernet networks; Feedback; Low-noise amplifiers; Optical amplifiers; Optical design; Optical receivers; Voltage;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537465
