Gigascale integration (GSI) beyond 2001

Opportunities for gigascale integration (GSI) beyond the year 2001 are governed by a hierarchy of limits whose levels are fundamental, material, device, circuit and system. Theoretical limits are elucidated in the power versus delay (Pt_d) plane for switching operations and in the square of the reciprocal length versus delay (L ^-2e) plane for transmission operations. The totality of practical limits is captured by three macrovariables; minimum feature size, chip area and number of transistors per minimum feature area. The singular metric which reveals the efficacy of a technology for GSI is the chip performance index (CPI) defined as the number of transistors per chip divided by the power-delay product of the technology. The CPI has increased by about 10¹³ since 1960 and is projected to increase still further by 10⁶ by 2020