The impact of new technology on soft error rates

This paper presents the impact of new microprocessor technology on microprocessor soft error rate (SER). The results are based on Oracle´s (formerly Sun Microsystems) neutron beam testing over the past several years. We describe how the tests were conducted and how the test results are used to influence microprocessor design. As microprocessor feature sizes decreased from 180nm to 65nm, memory error rates per bit decreased, but our data indicates a reversal of this trend at 40nm. Flop error rates still appear to be decreasing, even at a 28nm feature size We measure SER as a function of power supply voltage (Vdd) over a range of 1.2V down to 0.5V, and the data shows SER significantly increases as Vdd decreases. This result implies that dynamic voltage frequency scaling (DVFS), a commonly used microprocessor energy reduction technique, could cause a significant decrease in microprocessor reliability. The data also show that more energy-efficient transistors using back bias technique do not appear to significantly impact microprocessor reliability.