Thru-Wafer Interconnect for SOI-MEMS 3D Wafer-Level Hermetic Packaging

Author

Lin, Chiung-Wen ; Yang, Hsueh-An ; Wang, Wei Chung ; Fang, Weileun

Author_Institution

Nat. Tsing Hua Univ., Hsinchu

fYear

2007

fDate

10-14 June 2007

Firstpage

2111

Lastpage

2114

Abstract

This research reports a packaging approach for SOI-MEMS devices using through-wafer vias and anodic bonding technologies. Through-wafer vias are embedded inside the SOI wafers, and are realized using laser drilling and electroplating. These vias provide electrical signal paths to MEMS device, whereas isolate MEMS devices from outer environment. A high-strength hermetic sealing is then achieved after anodic bonding of this through-wafer vias embedded SOI wafer to a Pyrex 7740 glass. Moreover, the packaged SOI-MEMS chip is compatible with the surface mount technology, and performs a superior way for 3D heterogeneous integration.

Keywords

chip scale packaging; electroplating; hermetic seals; integrated circuit interconnections; laser beam machining; micromechanical devices; silicon-on-insulator; wafer bonding; wafer level packaging; wafer-scale integration; 3D heterogeneous integration; MEMS device; Pyrex 7740 glass; SOI-MEMS chip; anodic bonding technology; electroplating; laser drilling; through-wafer vias technology; wafer-level hermetic packaging; Drilling; Glass; Microelectromechanical devices; Micromechanical devices; Scanning electron microscopy; Semiconductor device packaging; Silicon on insulator technology; Surface-mount technology; Wafer bonding; Wafer scale integration; MEMS packaging; Through-wafer vias; heterogeneous integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Sensors, Actuators and Microsystems Conference, 2007. TRANSDUCERS 2007. International

Conference_Location

Lyon

Print_ISBN

1-4244-0842-3

Electronic_ISBN

1-4244-0842-3

Type

conf

DOI

10.1109/SENSOR.2007.4300582

Filename

4300582