Variation-resilient voltage generation for SRAM weak cell testing

Increasing process spread has made SRAM stability a major concern in SoC integration. Previous approaches to SRAM stability testing focused on the CUT but did not address the impact of variation on testing circuitry itself. This paper presents a very simple voltage generator scheme that considers controllability and observability of testing circuitry while dealing with process variations. The proposed design can be easily tuned with a bias voltage to combat variations. Experimental results with 0.18um technology show that voltage deviation within the range of ±2% can be achieved, which greatly increases the robustness of testing circuitry against variations.