• DocumentCode
    3380699
  • Title

    Challenges of electrostatic discharge (ESD) protection in emerging silicon nanowire technology

  • Author

    Liou, Juin J. ; Jiang, Chang ; Guang-Biao, Cao ; Gung, Chang ; Chia, Feng

  • Author_Institution
    Univ. of Central Florida, Orlando, FL, USA
  • fYear
    2011
  • fDate
    25-28 Oct. 2011
  • Firstpage
    256
  • Lastpage
    258
  • Abstract
    Electrostatic discharge (ESD) induced failures continue to be a major reliability concern in the semiconductor industry. Such a concern will in fact be intensified as the CMOS technology is scaling toward the 22-nm and beyond. This paper covers the issues and challenges pertinent to the design of electrostatic discharge (ESD) protection solutions of the emerging and increasingly important Si nanowire technology.
  • Keywords
    CMOS integrated circuits; electrostatic discharge; integrated circuit reliability; nanowires; semiconductor industry; silicon; CMOS technology; Si; electrostatic discharge protection; reliability concern; semiconductor industry; silicon nanowire technology; size 22 nm; Electric potential; Integrated circuits; Robustness;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC (ASICON), 2011 IEEE 9th International Conference on
  • Conference_Location
    Xiamen
  • ISSN
    2162-7541
  • Print_ISBN
    978-1-61284-192-2
  • Electronic_ISBN
    2162-7541
  • Type

    conf

  • DOI
    10.1109/ASICON.2011.6157170
  • Filename
    6157170
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3380699