Title :
A holistic approach to process co-optimization for through-silicon via
Author_Institution :
Silicon Syst. Group, Appl. Mater. Inc., Sunnyvale, CA, USA
Abstract :
As through-silicon via (TSV) technology transitions from development to production, several opportunities exist to co-optimize processes to ensure a wide process window while meeting cost targets and manufacturing robustness. Trade-offs in the via middle, via reveal, and via last integration schemes involving etch, CVD, PVD, ECD, CMP, and wafer support systems (carrier wafers) are addressed.
Keywords :
chemical mechanical polishing; chemical vapour deposition; optimisation; three-dimensional integrated circuits; CMP; CVD; ECD; PVD; TSV technology transitions; carrier wafers; holistic approach; manufacturing robustness; process co-optimization; through-silicon via; wafer support systems; Copper; Dielectrics; Silicon; Surface treatment; Through-silicon vias; Chemical vapor deposition (CVD); chemical-mechanical planarization (CMP); electrochemical deposition (ECD); etch; physical vapor deposition (PVD); through-silicon via (TSV);
Conference_Titel :
Reliability Physics Symposium (IRPS), 2011 IEEE International
Conference_Location :
Monterey, CA
Print_ISBN :
978-1-4244-9113-1
Electronic_ISBN :
1541-7026
DOI :
10.1109/IRPS.2011.5784529
