Title :
HV CMOS orientated variation-aware layout and robust solution
Author :
Cong, Gu ; Hong, Chen
Author_Institution :
Design Enable Group, Freescale Semicond. Ltd., Beijing, China
Abstract :
Ignoring variation causes final product yield loss while disclosure of any variation of silicon manufacturing will improve the speed of getting the new-product to market. This paper presents the variations from device layout orientation as observed through the foundry WAT data and correlation analysis versus HV CMOS device model corners and technology specs. A robust solution of variation elimination is also presented.
Keywords :
CMOS integrated circuits; elemental semiconductors; integrated circuit layout; silicon; HV CMOS device model; correlation analysis; device layout orientation; foundry WAT data; silicon manufacturing; variation elimination; variation-aware layout; CMOS integrated circuits; MOS devices;
Conference_Titel :
ASIC (ASICON), 2011 IEEE 9th International Conference on
Conference_Location :
Xiamen
Print_ISBN :
978-1-61284-192-2
Electronic_ISBN :
2162-7541
DOI :
10.1109/ASICON.2011.6157172
