A novel counter-based low complexity inner-product architecture for high speed inputs

This paper presents a new methodology of multiplierless implementation of inner-product computation. The inner-product computation is decomposed to form an architecture that facilitates an efficient serial accumulation of the 1´s in the partial product matrix of each multiplication of a pair of elements from the input vectors. The 1´s that appear at each partial product position are accumulated by a serial D flip flop (DFF) based 1´s counter. This accumulation stage reduces the column height of the partial product matrix by transforming L vertical bits to ⌊log₂ L⌋ + 1 horizontal bits at each coordinate of the partial product matrix. The counter outputs are further summed using carry save addition based on Dadda´s reduction algorithm followed by final carry propagating addition to obtain the final inner-product result. As the counter can operate at a frequency of 2 GHz when implemented on TSMC 0.18 μm CMOS process, the accumulation time is reduced significantly. With simpler partial product reduction tree, the hardware complexity is substantially reduced while the throughput is maintained to be comparable or better than many existing parallel inner-product computation architectures. The synthesis results of the proposed inner-product architecture for various inner-product lengths show that it has lower area-delay-product than many existing architectures.