A twin-tub CMOS using self-aligned channel-stop in conjunction with poly-buffer LOCOS for 1M/4M SRAM application

Author

Chen, M.-L. ; Juengling, W. ; Hillenius, S.J. ; Yang, T.S. ; Fu, C.C. ; Favreau, D.P. ; Powell, R.

Author_Institution

AT&T Bell Labs., Allentown, PA, USA

fYear

1991

fDate

22-24 May 1991

Firstpage

358

Lastpage

361

Abstract

Describes a simplified twin-tub process for high density SRAM application. A self-aligned channel-stop and punch-through implant along with poly-buffered LOCOS process improve the isolation and minimize the narrow width effect on the access transistors in the array. An additional deep boron implant through field oxide further reduces the spacing between the pull down drivers

Keywords

CMOS integrated circuits; SRAM chips; integrated circuit technology; 1 Mbit; 4 Mbit; CMOS; access transistors; field oxide; high density SRAM; isolation; narrow width effect; poly-buffer LOCOS; pull down drivers; punch-through implant; self-aligned channel-stop; twin-tub process; Boron; CMOS process; Capacitance; Conductivity; Driver circuits; Implants; Random access memory; Stress; Thermal degradation; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 1991. Proceedings of Technical Papers, 1991 International Symposium on

Conference_Location

Taipei

ISSN

1524-766X

Print_ISBN

0-7803-0036-X

Type

conf

DOI

10.1109/VTSA.1991.246732

Filename

246732

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3380803