The design of low leakage SRAM cell with high SNM

As the development of CMOS technology, the memory takes a great part in the entire chip area and becomes the main power contributor in the SOC system. SRAM which is the most used in on-chip memory for its low activity now consumes a lot of power while in standby mode because of the increasing number of transistors and scaling feature length. Therefore several analysis of traditional 6T transistor has been done and some design principles are given. At last, in this paper a 10T low leakage SRAM cell with high SNM based on SMIC 90nm CMOS technology has been introduced. The proposed SRAM cell saves about 88% leakage current and the SNM in read operation is enlarged 3.5 times and does not decrease in data retention. In order to reduce the sensing delay, a two-stage sense amplifier which turns the differential to single-ended is also proposed. By using this sense amplifier, the sensing delay is reduced to 46% when the load capacitance is 100fF compared with conventional voltage sense amplifier.