CMOS cell base implementation of the SPARC architecture

Author

Wang, S.T. ; Lai, S.J. ; Chou, Joe ; Tarn, H.Y. ; Chang, C.C. ; Tung, S.W. ; Ray, J.Y. ; Kuo, J.Y. ; Yang, L.M.

Author_Institution

Comput. Integrated Circuit Dept., CCL/ITRI, Hsinchu, Taiwan

fYear

1991

fDate

22-24 May 1991

Firstpage

334

Lastpage

337

Abstract

Presents an overview of the TA53017 processor which is the first implementation of the 32-bit RISC based scalable processor architecture (SPARC) CPU chip. The TA53017 (Integer Unit) was fabricated with TSMC´s 1.2 um double-metal CMOS technology and completed in the CCL/ITRI´s hierarchical cell-based design environment. It operates at a clock rate of 25 MHz and delivers an average performance of 10-15 MIPS, with an external cache and a floating-point coprocessor

Keywords

CMOS integrated circuits; cellular arrays; microprocessor chips; parallel architectures; reduced instruction set computing; 1.2 micron; 10 to 15 MIPS; 25 MHz; 32 bits; CCL/ITRI´s hierarchical cell-based design environment; RISC based scalable processor architecture; SPARC architecture; TA53017 processor; clock rate; double-metal CMOS technology; external cache; floating-point coprocessor; Adders; CMOS integrated circuits; CMOS technology; Computer architecture; Coprocessors; Logic design; Packaging; Pipelines; Registers; Workstations;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 1991. Proceedings of Technical Papers, 1991 International Symposium on

Conference_Location

Taipei

ISSN

1524-766X

Print_ISBN

0-7803-0036-X

Type

conf

DOI

10.1109/VTSA.1991.246737

Filename

246737