A study of dual-Vt configurations of an 8T SRAM cell in 45nm

Since the dual-threshold voltage assignment is an effective technique to reduce leakage power with negligible area overhead, we evaluate and compare the performance of an 8T SRAM cell in various dominant dual-V_t configurations in this paper, in order to provide the designer with a reasonable trade-off in SNM, leakage power, and delay for further different desired yields. According to simulation results, it is concluded that the configuration C8 has the highest SNM and high V_t Mnl can suppress the leakage current effectively. At last, the write and read delay time in different dual-V_t configurations are analyzed, and the reasons for delay variation are given.