DocumentCode :
3380958
Title :
Robust pad layout to improve wire bonding reliability
Author :
Kim, Kyoung-Hwan ; Min, Hong Kook ; Park, Se Yeoul ; Park, So Ra ; Yang, Seung Jin ; Shim, Byung Sup ; Kim, Yong Tae ; Han, Jeong-Uk
Author_Institution :
Syst. LSI Div., Samsung Electron., Yongin, South Korea
fYear :
2011
fDate :
10-14 April 2011
Abstract :
Different from the conventional study to improve the pad reliability against the peel-off, this study focuses on the probability that the peel-off could be originated from the perpendicular pushing down mechanical stress (PPMS) during the ball mounting process. Suggested in this paper are a new model which causes the peel-off and a new pad structure that overcomes the pad peel-off without any special procedures or changes in material or dimension. Three sets of layout patterns have been designed and fabricated in a 0.13 μm CMOS process. To assess the wire bonding quality, wire pulling tests (WPT) and evaluation of bonding power dependencies by means of wedge wire bonding are conducted. Additionally, FAMMOS simulator is adopted to verify the newly proposed pad structure.
Keywords :
CMOS integrated circuits; integrated circuit layout; integrated circuit modelling; integrated circuit reliability; lead bonding; stress analysis; CMOS process; FAMMOS simulator; ball mounting process; perpendicular pushing down mechanical stress; robust pad layout; size 0.13 mum; wire bonding reliability; wire pulling tests; Bonding; Force; Metals; Silicon; Stress; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Reliability Physics Symposium (IRPS), 2011 IEEE International
Conference_Location :
Monterey, CA
ISSN :
1541-7026
Print_ISBN :
978-1-4244-9113-1
Electronic_ISBN :
1541-7026
Type :
conf
DOI :
10.1109/IRPS.2011.5784539
Filename :
5784539
Link To Document :
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