Design of a single-ended cell based 65nm 32 × 32b 4R2W register file

This paper describes a 32×32b 4-read 2-write ported register file in 65nm CMOS. A single-ended read cell using pass gate is proposed, which supports a static read access on the read bit line. This read scheme avoids switching power when successive “0” or “1” emerges on the read bit line. An inverter isolator is added in read port, which improves the read static noise margin (SNM) dramatically. The cell array is divided into 4 banks with each bank 8 words. In this way, the capacities on the read bit line are cut down to 25% of that not banked, which benefits for both read power and latency. To reduce power further, clock gating is used to cut off active power when read or write operation is not necessary. Simulation results show that the read latency is 1.06ns with 12mW total power and 18 uW leakage power at 1.2V.