Title :
The designs of two-level pipelined systolic arrays for recursive digital filters with maximum throughput rate
Author :
Wen, Shih-Chieh ; Liu, Chi-Min ; Jen, Chein-Wei
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
Presents two-level pipelined systolic arrays for high throughput IIR filters. By combining the look-ahead schemes and the two-level pipelining technique, the VLSI architectures which support the maximum throughput rate and the strategies which make this rate possible are derived. Extending the results concluded from 1-D IIR filters, the authors also present high throughput rate realizations for 2-D IIR filters
Keywords :
VLSI; pipeline processing; systolic arrays; two-dimensional digital filters; 1D filters; 2D filters; IIR filters; VLSI architectures; look-ahead schemes; recursive digital filters; throughput rate; two-level pipelined systolic arrays; Computer architecture; Digital filters; Finite impulse response filter; IIR filters; Pipeline processing; Scattering; Synthetic aperture sonar; Systolic arrays; Throughput; Very large scale integration;
Conference_Titel :
VLSI Technology, Systems, and Applications, 1991. Proceedings of Technical Papers, 1991 International Symposium on
Conference_Location :
Taipei
Print_ISBN :
0-7803-0036-X
DOI :
10.1109/VTSA.1991.246740
