Title :
Addressing technique for parallel memory accessing in radix-2 FFT processors
Author :
Nakos, K. ; Reisis, D. ; Vlassopoulos, N.
Author_Institution :
Dept. of Phys., Nat. & Kapodistrian Univ. of Athens, Athens
fDate :
Aug. 31 2008-Sept. 3 2008
Abstract :
This paper presents an efficient technique for addressing in radix-2 FFT architectures. The novel addressing organization provides parallel load and store of the data involved in a radix-2 butterfly computation. The addressing scheme is based on a permutation of the FFT data, which leads to the minimization of the address generating circuit and the butterfly processor control. The paper proves the correctness of the technique and includes a FPGA implementation.
Keywords :
field programmable gate arrays; read-only storage; FPGA implementation; addressing technique; butterfly processor control; parallel memory accessing; radix-2 FFT processors; radix-2 butterfly computation; Computer architecture; Concurrent computing; Counting circuits; Distributed computing; Laboratories; Minimization; Physics; Process control; Table lookup; Telecommunication computing;
Conference_Titel :
Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on
Conference_Location :
St. Julien´s
Print_ISBN :
978-1-4244-2181-7
Electronic_ISBN :
978-1-4244-2182-4
DOI :
10.1109/ICECS.2008.4674789
