Architecture for reconfigurable MIMO detector and its FPGA implementation

Multiple Input Multiple Output (MIMO) system is a key technology for future high speed wireless communication standards like 802.11n, WIGWAM, and WiMax. These standards require support for multiple modulation and coding schemes. Hence, the receiver hardware should be able to accomodate these schemes preferably on a single reconfigurable architecture. Current MIMO detector implementations are constrained by the throughput and dynamic reconfigurability requirements. This paper presents an FPGA implementation of a novel MIMO detector architecture which addresses these issues. The proposed design is able to reconfigure on the fly without significant latency overhead and delivers quasi-optimal Bit Error Rate(BER). The regularity of the architecture makes it suitable for a highly parallel and pipelined implementation. Our design is implemented on a Xilinx Virtex-4 FPGA, and has a parallelism factor of four with four pipeline stages. Additionally, the design does not use multipliers, and has minimal control overhead(0.3%). Our detector achieves a throughput of 280 Mbps for QPSK, 140 Mbps for 16-QAM, and 52.5 Mbps for 64-QAM. The detector, with a non-processor based control unit, has many qualities of a systolic architecture which makes it highly suitable for ASIC implementation.