Detection of inter-port bridging faults in dual-port memories

This paper presents an approach and test sequence to detect inter-port bridging faults in dual-port memories. Unlike other approaches we model a fault as a four-way bridging fault which is more reflective of a real defect. In our test approach, we consider word- and bit- line bridges, both in structure and in functional modes. Further, faults for all scenarios namely, read-read, write-write, and read-write ports are considered. We also propose the use of additional logic, three wide-OR gates, to detect certain inter-port faults that may remain undetected otherwise. Our approach achieves 100% coverage of all inter-port bridging faults.