Title :
Standard cell design of a low-leakage flip-flop with gate-length biasing
Author :
Hu, Jianping ; Wang, Jun
Author_Institution :
Fac. of Inf. Sci. & Technol., Ningbo Univ., Ningbo, China
Abstract :
In this paper, a low-power flip-flop standard cell with gate-length biasing technology is introduced into SMIC 130nm CMOS libraries for low-leakage applications. The flip-flop standard cell based on the transmission gate with master-slave structure is optimized to achieve low energy delay product (EDP) by using gate-length biasing. The layout, abstract design and standard-cell characters of the low-power flip-flop are also described.
Keywords :
CMOS logic circuits; flip-flops; integrated circuit layout; logic design; low-power electronics; SMIC CMOS library; abstract design; gate length biasing technology; integrated circuit layout; low energy delay product; low leakage flip-flop; master-slave structure; standard cell design; transmission gate; Capacitance; Flip-flops; Frequency synthesizers; Libraries; Logic gates; Routing; Switches;
Conference_Titel :
ASIC (ASICON), 2011 IEEE 9th International Conference on
Conference_Location :
Xiamen
Print_ISBN :
978-1-61284-192-2
Electronic_ISBN :
2162-7541
DOI :
10.1109/ASICON.2011.6157196
