Debugging methodology and timing analysis in CDC solution

As the design complexity of system LSI increasing, the number of clock domains also increases for system LSI designs. Due to the sheer volume of crossing signals and the different ways of crossing implementation, verifying clock domain crossings (CDC) has become a very important yet challenging task. Specialized CDC verification solution needs to be deployed to perform analysis of the design to accurately detect CDC issues as well as efficiently debug the root causes of these problems. This paper describes a case study on CDC verification for FPGA designs using Meridian CDC, Real Intent´s clock domain crossing verification solution.