Title :
Efficient test generation with maximal crosstalk-induced noise using unconstrained aggressor excitation
Author :
Eggersgluss, Stephan ; Tille, Daniel ; Drechsler, Rolf
Author_Institution :
Inst. of Comput. Sci., Univ. of Bremen, Bremen, Germany
fDate :
May 30 2010-June 2 2010
Abstract :
The influence of crosstalk noise grows as the feature sizes in modern designs decrease. Crosstalk-induced effects are able to cause major timing violations, especially if multiple aggressors affect certain lines. However, conventional Automatic Test Pattern Generation (ATPG) algorithms for delay test do not consider these effects during test generation. This increases the possibility that chips which passed the testing phase might fail due to crosstalk-induced effects. In this paper, we propose a new efficient ATPG approach for generating delay tests considering crosstalk-induced effects using Boolean Satisfiability (SAT). Previous approaches used a two-step procedure to increase the crosstalk-induced noise. As a result, the search space is highly restricted. In contrast, the proposed approach is able to do test generation and excite multiple aggressors in one step. By this, more aggressor combinations can be found and the generated test potentially induce more crosstalk noise on the victim. In order to maximize the crosstalk-induced effects of the test, an exact branch-and-bound algorithm and a static aggressor ordering heuristic are applied and compared. Experimental results demonstrate the efficiency and effectiveness of the approach.
Keywords :
Boolean functions; automatic test pattern generation; circuit noise; computability; crosstalk; tree searching; Boolean satisfiability; automatic test pattern generation; branch-and-bound algorithm; maximal crosstalk-induced noise; static aggressor; test generation; timing violations; unconstrained aggressor excitation; Automatic test pattern generation; Automatic testing; Circuit testing; Computer science; Crosstalk; Delay effects; Noise generators; Switches; Test pattern generators; Timing;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537503