DocumentCode
3381283
Title
On integrating control algorithms for buffer management and concurrency for parallel transaction processing systems
Author
Wang, Shiwei ; Hsu, Yarusun
Author_Institution
Aiken Comput. Lab., Harvard Univ., Boston, MA, USA
fYear
1991
fDate
22-24 May 1991
Firstpage
433
Lastpage
438
Abstract
The performance of multi-processor based data sharing complex for transaction processing can be enhanced through the use of an integrated concurrency-coherency-recovery protocol. This protocol, combined with the use of shared main memory buffer, can allow early commit of transaction updates, reduce multi-system coupling overhead, and eliminate the unnecessary disk updates in transaction processing in normal time. Results obtained from performance simulation study show a significant improvement in the maximum transaction throughput can be sustained if this integrated protocol is used
Keywords
concurrency control; multiprocessing systems; protocols; storage management; transaction processing; buffer management; concurrency; disk updates; integrated concurrency-coherency-recovery protocol; integrated protocol; multi-processor based data sharing complex; multi-system coupling overhead; parallel transaction processing systems; shared main memory buffer; transaction updates; Communication system control; Concurrent computing; Decision support systems; Degradation; Model driven engineering;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems, and Applications, 1991. Proceedings of Technical Papers, 1991 International Symposium on
Conference_Location
Taipei
ISSN
1524-766X
Print_ISBN
0-7803-0036-X
Type
conf
DOI
10.1109/VTSA.1991.246756
Filename
246756
Link To Document