An optimum mapping of IPs for On-Chip Network design based on the minimum latency constraint

A new chip design paradigm, so called network on chip, has been introducing based on the demand of integration of many heterogeneous semiconductor intellectual property (IP) blocks. The network on chip design not only requires the good performance but also the minimization of several physical constraints such that the network latency, the used area as well as the power consumption of design. This paper analyzes the average latency of heterogeneous network on chip architectures in which the shortest path routing algorithm is applied. This average latency includes the queuing latency and the wire latency, and is calculated for general cases of allocating IPs onto a fixed generic switching architecture as 2-D mesh. With different allocation schemes of IPs, the network has different average latencies. Hence, this article presents an optimal search that adopts the Branch and Bound algorithm to find out the optimal mapping scheme to achieve the minimal network latency. This algorithm automatically map the desired IPs onto the target network on chip architecture with the criteria of lowest network latency. The optimal latency, as our research target, allows us to achieve the design with low power consumption as well. We also carry out the experiment for on chip multiprocessor network application. The results shows that 36.5% and 40.3% of network latency are saved with the optimized allocation scheme for the cases of 3 x 3 and 4 x 4 Mesh architectures of on chip multiprocessor network application, respectively.