• DocumentCode
    3381581
  • Title

    An effecient level-shifter floorplanning method for Multi-voltage design

  • Author

    Zhang, Xiaolin ; Lin, Zhi ; Chen, Song ; Yoshimura, Takeshi

  • Author_Institution
    Grad. Sch. of IPS, Waseda Univ., Kitakyushu, Japan
  • fYear
    2011
  • fDate
    25-28 Oct. 2011
  • Firstpage
    421
  • Lastpage
    424
  • Abstract
    Nowdays, Low-power design, especially Multi-voltage design becomes a popular and efficient way to reduce both dynamic power and static power. In this paper, we propose an efficient method of level-shifter floorplanning for a given multi-voltage design. This method is a two stage optimization method. First, for a given voltage island and its sequence pair representation, we greedily pre-place level-shifters into white-spaces of multi-voltage island based sequence-pair representation. Then, we employ a modified IARFP [1] algorithm to re-optimize the positions of level-shifters. Experimental results show that, the proposed two stage level-shifter floorplanner is efficient for post multi-voltage island optimization.
  • Keywords
    circuit layout; low-power electronics; simulated annealing; level-shifter floorplanning method; low-power design; multivoltage design; two stage optimization method; Application specific integrated circuits; Chirp; Optimization; Level-Shifter; Multi-voltage design; Voltage-Island;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC (ASICON), 2011 IEEE 9th International Conference on
  • Conference_Location
    Xiamen
  • ISSN
    2162-7541
  • Print_ISBN
    978-1-61284-192-2
  • Electronic_ISBN
    2162-7541
  • Type

    conf

  • DOI
    10.1109/ASICON.2011.6157211
  • Filename
    6157211